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LTC1698 Isolated Secondary Synchronous Rectifier Controller
FEATURES
s s s s s s s s s s s
DESCRIPTIO
High Efficiency Over Wide Load Current Range 0.8% Output Voltage Accuracy Dual N-Channel MOSFET Synchronous Drivers Pulse Transformer Synchronization Optocoupler Feedback Driver Programmable Current Limit Protection 5% Margin Output Voltage Adjustment Adjustable Overvoltage Fault Protection Power Good Flag Auxiliary 3.3V Logic Supply Available in 16-Lead SSOP and SO Packages
The LTC (R)1698 is a precision secondary-side forward converter controller that synchronously drives external N-channel MOSFETs. It is designed for use with the LT(R)3781 primary-side synchronous forward converter controller to create a completely isolated power supply. The LT3781 synchronizes the LTC1698 through a small pulse transformer and the LTC1698 drives a feedback optocoupler to close the feedback loop. Output accuracy of 0.8% and high efficiency over a wide range of load currents are obtained. The LTC1698 provides accurate secondary-side current limit using an external current sense resistor. The input voltage at the MARGIN pin provides 5% output voltage adjustment. A power good flag and overvoltage input are provided to ensure proper power supply conditions. An auxiliary 3.3V logic supply is included that supplies up to 10mA of output current.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s s
48V Input Isolated DC/DC Converters Isolated Telecommunication Power Systems Distributed Power Step-Down Converters Industrial Control Systems Automotive and Heavy Equipment
TYPICAL APPLICATIO
VIN 36V to 72V
L1
+
Q1 D1 VDD BIAS COUT
+
1 10 VDD CG FG ISNS
R1
R2
T1 Q4 Q2 RPRISEN RSECSEN 11 CSG TG BG CSYNC 15 T2 D2 Q3 2 16 12
*
PWRGD 8 VFB CFB VCOMP 6
LTC1698
ISNSGND SYNC
ICOMP OVPIN
13 9
RCILM
*
SG
RSYNC MARGIN
7
VMARGIN VAUX 3.3V 10mA
LT3781
RK REF VFB RE CK
5
OPTODRV PGND 3
VAUX GND 4
14 O.1F
1681 F01
VC RF
+ -
CF
ISOLATION BOUNDARY
PLEASE REFER TO FIGURE 12 IN THE TYPICAL APPLICATIONS SECTION FOR THE COMPLETE 3.3V/15A APPLICATION SCHEMATIC
Figure 1. Simplified 2-Transistor Isolated Forward Converter
1698f
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VOUT RC CC R5 CCILM R4
U
U
* *
1
LTC1698
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW VDD CG PGND GND OPTODRV VCOMP MARGIN VFB 1 2 3 4 5 6 7 8 16 FG 15 SYNC 14 VAUX 13 ICOMP 12 ISNS 11 ISNSGND 10 PWRGD 9 OVPIN
VDD, PWRGD ....................................................... 13.2V Input Voltage MARGIN, VFB, OVPIN, ISNSGND, ISNS ... - 0.3V to 5.3V SYNC ..................................................... - 14V to 14V Output Voltage VCOMP, ICOMP (Note 2) ......................... - 0.3V to 5.3V Power Dissipation .............................................. 500mW Operating Temperature Range LTC1698E (Note 3) ............................ - 40C to 85C LTC1698I ........................................... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1698EGN LTC1698ES LTC1698IGN LTC1698IS GN PART MARKING 1698 1698I
GN PACKAGE S PACKAGE 16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO
TJMAX = 125C, JA = 130C/W (GN) TJMAX = 125C, JA = 110C/W (SO)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VDD VUVLO IVDD PARAMETER Supply Voltage Undervoltage Lockout VDD Supply Current
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 8V, unless otherwise noted. (Note 4)
CONDITIONS
q
MIN 6
TYP 8 4
MAX 12.6
UNITS V V
VFB, OVPIN, VISNS, VISNSGND = 0V, CFG = CCG = 1000pF, CVAUX = 0.1F, VSYNC = 0V fSYNC = 100kHz (Note 5)
q
1.8 5.0 1.223 1.215 1.233 1.233 0.05 1.65 16.5
4
MARGIN and Error Amplifier VFB IVFB VMARGIN RMARGIN VFB GERR BWERR VCLAMP IVCOMP OPTODRV GOPTO BWOPTO VOPTOHIGH IOPTOSC Opto Driver DC Gain Opto Driver Unity-Gain Bandwidth Opto Driver Output High Voltage Opto Driver Output Short-Circuit Current OVPIN, VISNS, VISNSGND = 0V No Load (Note 6) VFB, OVPIN, VISNSGND = 0V, VISNS = - 50mV, IOPTODRV = -10mA OVPIN, VISNSGND, VISNS = 0V, VFB = 1.233V
q q q
Feedback Voltage Feedback Input Current MARGIN Voltage MARGIN Input Resistance Feedback Voltage Adjustment Error Amplifier Open-Loop DC Gain Error Amplifier Unity-Gain Bandwidth Error Amplifier Output Clamp Voltage Error Amplifier Source Current Error Amplifier Sink Current
MARGIN = Open, VCOMP = 1V (Note 7)
q
1.243 1.251 1
VFB = 1.233V MARGIN = Open VMARGIN = 3.3V VMARGIN = 0V VCOMP = 0.8V to 1.2V, Load = 2k, 100pF No Load (Note 6) VFB = 0V VFB = 0V VFB = 5V, VCOMP = 1.233V
q
q q q
4 -6 65
5 -5 90 2 2
6 -4
q q
3 4.75
- 25 7 5 1
- 10
5.25
4 - 50
5 - 25 - 10
2
U
W
U
U
WW
W
mA mA V V A V k % % dB MHz V mA mA V/V MHz V mA
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LTC1698
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VAUX VAUX Auxiliary Supply Voltage CONDITIONS
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 8V, unless otherwise noted. (Note 4)
MIN
q q q q
TYP 3.320 0.05 0.05
MAX 3.465 1 1 - 23.0 - 22.5 - 120 - 80 280 370 5
UNITS V A A mV mV A A A A millimho dB
CVAUX = 0.1F, ILOAD = 0mA to 10mA, VDD = 7V to 12.6V VISNSGND = 0V VISNS = 0V VICOMP = 2.5V, VISNSGND = 0V VISNSGND = 0V, VISNS = - 0.3V, VICOMP = 2.5V (Note 8)
3.135
Current Limit Amplifier IISNSGND ISNSGND Input Current IISNS ISNS Input Current VILIMTH Current Limit Threshold (VISNS - VISNSGND) IICOMP ICOMP Source Current ICOMP Sink Current gmILIM GICOMP Current Limit Amplifier Transconductance Current Limit Amplifier Open-Loop DC Gain Percent Below VFB Power Good Sink Current Power Good Output Low Voltage
- 27.0 - 27.5 - 280 - 370 120 80 2.2 48
- 25 - 25 - 200 - 200 200 200 3.5 60
q
VISNSGND = 0V, VISNS = 0.3V, VICOMP = 2.5V (Note 8)
q
VISNSGND = 0V, VICOMP = 2.5V, IICOMP = 10A VICOMP = 2.5V, No Load
q q
PWRGD and OVP Comparators VPWRGD IPWRGD VOL VFB , MARGIN = Open (Note 9) VFB = 2V VFB = 0V IPWRGD = 3mA, VFB = 0V VFB = VISNS = VISNSGND = 0V, OVPIN (Note 9) VOVPIN = 1.233V VFB VFB VOVPIN , COPTODRV = 0.1F
q q q q q q q q q q q
-9 10
-6
-3 10 0.4
% A mA V V A ms ms s V V A kHz ns ns ns
VOVPREF OVPIN Threshold IOVPIN OVPIN Input Bias Current tPWRGD tOVP Power Good Response Time Power Bad Response Time Overvoltage Response Time
1.18 1 0.5
1.233 0.1 2 1 5
1.28 1 5 2.5 20 2.2 -1 50 400 90 40
SYNC and Drivers VPT SYNC Input Positive Threshold VNT ISYNC fSYNC td tSYNC tr, tf tDDIS SYNC Input Negative Threshold SYNC Input Current SYNC Frequency Range SYNC Input to Driver Output Delay Minimum SYNC Pulse Width Driver Rise and Fall Time Driver Disable Time-Out VSYNC = 10V CFG = CCG = 1000pF, VSYNC = 5V CFG = CCG = 1000pF, fSYNC = 100kHz, VSYNC = 5V fSYNC = 100kHz, VSYNC = 10V (Note 6) CFG = CCG = 1000pF, fSYNC = 100kHz, VSYNC = 5V, 10% to 90% CFG = CCG = 1000pF, fSYNC = 100kHz, VSYNC = 5V Measured from CG (Note 10)
1 - 2.2 50
1.6 -1.6 1 40
q q q q q
75 10
q
10
15
20
s
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. All voltages refer to GND. Note 2: The LTC1698 incorporates a 5V linear regulator to power internal circuitry. Driving these pins above 5.3V may cause excessive current flow. Guaranteed by design and not subject to test. Note 3: The LTC1698E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. For guaranteed performance to specifications over the -40C to 85C range, the LTC1698I is available. Note 4: All currents into device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified. For applications with VDD < 7V, refer to the Typical Performance Characteristics.
Note 5: Supply current in active operation is dominated by the current needed to charge and discharge the external FET gates. This will vary with the LTC1698 operating frequency, supply voltage and the external FETs used. Note 6: This parameter is guaranteed by correlation and is not tested. Note 7: VFB is tested in an op amp feedback loop which servos VFB to the internal bandgap voltage. Note 8: The current comparator output current varies linearly with temperature. Note 9: The PWRGD and OVP comparators incorporate 10mV of hysteresis. Note 10: The driver disable time-out is proportional to the SYNC period within the frequency synchronization range.
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LTC1698 TYPICAL PERFOR A CE CHARACTERISTICS
VFB vs Temperature
1.248 VDD = 8V
1.248
1.242 1.236
VFB (V)
VFB (V)
VFB (V)
1.230
1.224
1.218 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
1698 G01
ISNS Threshold vs Temperature
-22.5 -23.0 -23.5 VDD = 8V -22.5 -23.0 -23.5
ISNS THRESHOLD (mV)
ISNS THRESHOLD (mV)
-24.5 -25.0 -25.5 -26.0
-24.5 -25.0 -25.5 -26.0
gmILIM (millimho)
-24.0
-26.5 -27.0 -27.5 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
1698 G04
OVPIN Threshold vs Temperature
1.28 VDD = 8V
1.26
1.26
OVPIN THRESHOLD (V)
POWER GOOD THRESHOLD (V)
OVPIN THRESHOLD (V)
1.24
1.22
1.20
1.18 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
1698 G07
4
UW
VFB vs VDD
TA = 25C
1.295 1.282
VFB vs VMARGIN
VDD = 8V TA = 25C 5 4 3 2 1 0 -1 -2 -3 -4 0 0.33 0.66 0.99 1.32 1.65 1.98 2.31 2.64 2.97 3.3 VMARGIN (V)
1698 G03
1.242
1.270 1.258
1.236
1.245 1.233 1.221 1.208
VFB (%)
1.230
1.224
1.196 1.184
1.218 5 6 7 8 9 10 VDD (V) 11 12 13 14
1.171
-5
1698 G02
ISNS Threshold vs VDD
TA = 25C 5.0 4.6 4.2 3.8 3.4 3.0 2.6
Current Limit Amplifier gm vs Temperature
VDD = 8V
-24.0
-26.5 -27.0 -27.5 5 6 7 8 9 10 VDD (V) 11 12 13 14
2.2 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
1698 G06
1698 G05
OVPIN Threshold vs VDD
1.28 TA = 25C
1.196
Power Good Threshold vs Temperature
VDD = 8V -3.0
1.181
-4.2
1.24
1.166
-5.4
VFB (%)
1.22
1.152
-6.6
1.20
1.137
-7.8
1.18 5 6 7 8 9 10 VDD (V) 11 12 13 14
1.122 -50 -25
0
-9.0 25 50 75 100 125 150 TEMPERATURE (C)
1698 G09
1698 G08
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LTC1698 TYPICAL PERFOR A CE CHARACTERISTICS
VAUX vs Temperature
3.465 VDD = 8V 3.424 ILOAD = 0mA 3.383
VAUX (V)
VAUX (V)
3.300 3.259 3.218 3.176 3.135 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
1698 G10
3.300 3.259 3.218 3.176 3.135 5 6 7 8 9 10 VDD (V) 11 12 13 14
VAUX (V)
3.341
VAUX Short-Circuit Current vs Temperature
0 VDD = 8V 0
VAUX SHORT-CIRCUIT CURRENT (mA)
VAUX SHORT-CIRCUIT CURRENT (mA)
-10
-10
OPTO DRIVER OUTPUT VOLTAGE (V)
-20
-30
-40
-50 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
1698 G13
Maximum OPTO Driver Output Voltage vs Load Current
MAXIMUM OPTO DRIVER OUTPUT VOLTAGE (V)
MAXIMUM OPTO DRIVER OUTPUT VOLTAGE (V)
OPTO DRIVER SHORT-CIRCUIT CURRENT (mA)
8
6
4
2 TA = 25C VCOMP = 0V 0 1 2 345678 LOAD CURRENT (mA) 9 10
0
UW
VDD = 10V VDD = 8V VDD = 7V VDD = 6V VDD = 5V
VAUX vs Line Voltage
3.465 VDD = 8V 3.424 ILOAD = 0mA 3.383 3.341
3.465
VAUX vs Load Current
VDD = 8V 3.424 TA = 25C 3.383 3.341 3.300 3.259 3.218 3.176 3.135 0 1 2 345678 LOAD CURRENT (mA) 9 10
1698 G11
1698 G12
VAUX Short-Circuit Current vs VDD
TA = 25C 3.030 3.024 3.018 3.012 3.006 3.000 2.994 2.988 2.982 2.976 2.970
Opto Driver Load Regulation
VDD = 8V TA = 25C 1.0 0.8 0.6 0.4
PERCENT (%)
-20
0.2 0 -0.2 -0.4 -0.6 -0.8 0 1 2 345678 LOAD CURRENT (mA) 9 10 -1.0
-30
-40
-50 5 6 7 8 10 VDD (V) 9 11 12 13 14
1698 G14
1698 G15
Maximum OPTO Driver Output Voltage vs Temperature
8 VDD = 10V
Opto Driver Short-Circuit Current vs Temperature
-10 VDD = 8V -15 VOPTODRV = 1.233V -20 -25 -30 -35 -40 -45 -50 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
1698 G16
6
VDD = 8V VDD = 7V
4
VDD = 6V VDD = 5V
2 VCOMP = 0V IOPTODRV = -10mA 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
1698 G23
1698 G22
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LTC1698 TYPICAL PERFOR A CE CHARACTERISTICS
IVDD vs SYNC Frequency
50 45 40 35
IVDD (mA)
SYNC POSITIVE THRESHOLD (V)
SYNC POSITIVE THRESHOLD (V)
VDD = 8V TA = 25C
CFG = CCG = 4700pF CFG = CCG = 3300pF
30 25 20 15 10 5 0
CFG = CCG = 2200pF
CFG = CCG = 1000pF
50 100 150 200 250 300 350 400 450 500 fSYNC (kHz)
1698 G19
Opto Driver Short-Circuit Current vs VDD
OPTO DRIVER SHORT-CIRCUIT CURRENT (mA)
0 TA = 25C VOPTODRV = 1.233V 20 18 16 14
-10
IVDD (mA)
10 8 6 CFG = CCG = 2200pF CFG = CCG = 1000pF
VUVLO (V)
-20
-30
-40
-50 5 6 7 8 10 VDD (V) 9 11 12 13 14
Driver Rise, Fall and Propagation Delay vs Driver Load
90 80 70 60 TIME (ns) tf CG, FG tPHL tr VDD = 8V TA = 25C CG, FG tPLH 90 80 70 60
DRIVER DISABLE TIME-OUT tDISS (s)
t d (ns)
50 40 30 20 10 0 0 2000
6000 4000 DRIVER LOAD (pF)
6
UW
1698 G17
SYNC Positive Threshold vs Temperature
2.25 VDD = 8V
SYNC Positive Threshold vs VDD
2.20 TA = 25C
2.00
1.96
1.75
1.72
1.50
1.48
1.25
1.24
1.00 -50 -25
1.00
0 25 50 75 100 125 150 TEMPERATURE (C)
1698 G20
5
6
7
8
9 10 VDD (V)
11
12
13
14
1698 G21
IVDD vs VDD
5 TA = 25C fSYNC = 100kHz CFG = CCG = 4700pF 4
Undervoltage Lockout Threshold vs Temperature
CFG = CCG = 3300pF
12
3
2
4 2 0 5 6
1
7
8
9 10 VDD (V)
11
12
13
14
0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
1698 G24
1698 G18
SYNC Input to Driver Output Delay vs Temperature
VDD = 8V CCG = CFG = 1000pF fSYNC = 100kHz 30 25 20 15 10
Driver Disable Time-Out vs SYNC Frequency
VDD = 8V TA = 25C tDISS x fSYNC 2.2
NORMALIZED DRIVER DISABLE TIME-OUT tDISS x fSYNC
2.0 1.8 1.6 1.4 tDISS 1.2 1.0 50 100 150 200 250 300 350 400 450 500 fSYNC (kHz)
1698 G27
50 40 30 20 10
CG, FG tPLH CG, FG tPHL
5 0
8000
10000
0 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
1698 G26
1698 G25
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LTC1698
PI FU CTIO S
VDD (Pin 1): Power Supply Input. For isolated applications, a simple rectifier from the power transformer is used to power the chip. This pin powers the opto driver, the VAUX supply and the FG and CG drivers. An internal 5V regulator powers the remaining circuitry. VDD requires an external 4.7F bypass capacitor. CG (Pin 2): Catch Gate Driver. If SYNC slews positive, CG pulls high to drive an external N-channel MOSFET. CG draws power from the VDD pin and swings between VDD and PGND. PGND (Pin 3): Power Ground. Connect PGND to a low impedance ground plane in close proximity to the ground terminal of the external current sensing resistor. GND (Pin 4): Logic and Signal Ground. GND is referenced to the internal low power circuitry. Careful board layout techniques must be used to prevent corruption of signal ground reference. Connect GND and PGND together directly at the LTC1698. OPTODRV (Pin 5): Optocoupler Driver Output. This pin drives a ground referenced optocoupler through an external resistor. If VFB is low, OPTODRV pulls low. If VFB is high, OPTODRV pulls high. This optocoupler driver has a DC gain of 5. During overvoltage or overcurrent conditions, OPTODRV pulls high. The output is capable of sourcing 10mA of current and will drive an external 0.1F capacitive load and is short-circuit protected. VCOMP (Pin 6): Error Amplifier Output. This error amplifier is able to drive more than 2k and 100pF of load. The internal diode connected from VFB to VCOMP reduces OPTODRV recovery time under start-up conditions. MARGIN (Pin 7): Current Input to Adjust the Output Voltage Linearly. The MARGIN pin connects to an internal 16.5k resistor. The other end of this resistor is regulated to 1.65V. Connecting MARGIN to a 3.3V logic supply sources 100A of current into the chip and moves the output voltage 5% higher. Connecting MARGIN to 0V sinks 100A out of the pin and moves the regulated output voltage 5% lower. The MARGIN pin voltage does not affect the PWRGD and OVPIN trip points. VFB (Pin 8): Feedback Voltage. VFB senses the regulated output voltage through an external resistor divider. The VFB pin is servoed to the reference voltage of 1.233V under closed-loop conditions. An RC network from VFB to VCOMP compensates the feedback loop. If VFB goes low, VCOMP pulls high and OPTODRV goes low. OVPIN (Pin 9): Overvoltage Input. OVPIN is a high impedance input to an internal comparator. The threshold of this comparator is set to 1.233V. If the OVPIN potential is higher than the threshold voltage, OPTODRV pulls high immediately. Use an external RC lowpass filter to prevent noisy signals from triggering this comparator. PWRGD (Pin 10): Power Good Output. This is an opendrain output. PWRGD floats if VFB is above 94% of the nominal value for more than 2ms. PWRGD pulls low if VFB is below 94% of the nominal value for more than 1ms. The PWRGD threshold is independent of the MARGIN pin potential. ISNSGND (Pin 11): Current Sense Ground. Connect to the positive side of the sense resistor, normally grounded. ISNS (Pin 12): Current Sense Input. Connect to the negative side of the sense resistor through an external RC lowpass filter. This pin normally sees a negative voltage, which is proportional to the average load current. If current limit is exceeded, OPTODRV pulls high. ICOMP (Pin 13): Current Amplifier Output. An RC network at this pin compensates the current limit feedback loop. Referencing the RC to VOUT controls output voltage overshoot on start-up. This pin can float if current limit loop compensation is not required. VAUX (Pin 14): Auxiliary 3.3V Logic Supply. This pin requires a 0.1F or greater bypass capacitor. This auxiliary power supply can power external devices and sources 10mA of current. Internal current limiting is provided. SYNC (Pin 15): Drivers Synchronization Input. A negative voltage slew at SYNC forces FG to pull high and CG to pull low. A positive voltage slew at SYNC resets the FG pin and CG pulls high. If SYNC loses its synchronization signal for more than the driver disable time-out interval, both the forward and catch drivers output are forced low. The SYNC circuit accepts pulse and square wave signals. The minimum pulse width is 75ns. The synchronization frequency range is between 50kHz to 400kHz. FG (Pin 16): Forward Gate Driver. If SYNC slews negative, FG goes high. FG draws power from VDD and swings between VDD and PGND.
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LTC1698
BLOCK DIAGRA
14
15
7
5
10
VFB
0.94VREF
OPERATIO
(Refer to Block Diagram)
The LTC1698 is a secondary-side synchronous rectifier controller designed to work with the LT3781 primary-side synchronous controller chip to form an isolated synchronous forward converter. This chip set uses a dual transistor forward topology that is predominantly used in distributed power supply systems where isolated low voltages are needed to power complex electronic equipment. The primary stage is a current mode, fixed frequency forward converter and provides the typical PWM operation. A power transformer is used to provide the functions of input/output isolation and voltage step-down to achieve the required low output voltage. Instead of using typical
8
+
-
W
1 VDD VAUX AUX GEN VCC GEN VCC SYNC IN CG MARGIN RMARGIN I-TO-V CONVERTER 2 FG 16 SYNC BANDGAP VREF 5% VREF
+
OPTODRV OPTO
-
100k
20k ERR
+ -
VFB VCOMP 8 6 11
PWRGD
MPWRGD
+
MILIM RILIM 3k PWRGD ROVP 3k OVP ILIM 25mV
ISNSGND
-
+
ISNS ICOMP
12 13
+ -
VREF OVPIN
9
1698 BD
U
Schottky diodes, synchronous rectification on the secondary offers isolation with high efficiency. It supplies high power without the need of bulky heat sinks, which is often a problem in any space constrained application. The LTC1698 not only provides synchronous drivers for the external MOSFETs, it comes with other housekeeping functions performed on the secondary side of the power supply, all within a single integrated controller. Figure 1 shows the typical chip-set application. Upon power up, the LTC1698's VDD input is low, the gate drivers TG and BG are both at the ground potential. The secondary forward and
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LTC1698
OPERATIO
catch MOSFETs Q3 and Q4 are off. As soon as transistors Q1 and Q2 turn on, the flux in the power transformer T1 forces the body diodes of Q3 and Q4 to conduct, and the whole circuit starts like a conventional forward converter. At the same time, the LTC1698 VDD potential ramps up quickly through the VDD bias circuitry. Once the VDD voltage exceeds 4.0V, the LTC1698 enables its drivers and enters synchronous operation. The pulse transformer T2 synchronizes the primary and secondary MOSFET drivers. In a typical conversion cycle, the primary MOSFETs Q1 and Q2 turn on simultaneously. SG goes low and generates a negative spike at the LTC1698 SYNC input through the pulse transformer. The LTC1698 forces FG to turn on and CG to turn off. Power is delivered to the load through the transformer T1 and the inductor L1. At the beginning of the next phase in which Q1 and Q2 turn off, SG goes high, SYNC sees a positive spike, the MOSFET Q3 shuts off, Q4 conducts and allows continuous current to flow through the inductor L1. The capacitor COUT filters the switching waveform to provide a steady DC output voltage for the load. The LTC1698 error amplifier ERR senses the output voltage through an external resistor divider and regulates the VFB pin potential to the 1.233V internal bandgap voltage. An external RC network across the VFB and VCOMP pins frequency compensates the error amplifier feedback. The opto driver amplifies the voltage difference between the VCOMP pin and the bandgap potential, driving the external optocoupler diode with an inverting gain of 5. The optocoupler feeds the amplified output error signal to the primary controller and closes the forward converter voltage feedback loop. Under start-up conditions, the internal diode across the LTC1698 error amplifier clamps the VCOMP pin. This speeds up the opto driver recovery time by reducing the negative slew rate excursion at the COMP pin. The forward converter output voltage can be easily adjusted. The potential at the MARGIN pin is capable of
U
(Refer to Block Diagram)
forcing the error amplifier reference voltage to move linearly by 5%. The internal RMARGIN resistor converts the MARGIN voltage to a current and linearly controls the offset of the error amplifier. Connecting the MARGIN pin to 3.3V increases the VFB voltage by 5%, and connecting the MARGIN pin to 0V reduces VFB by 5%. With the MARGIN pin floating, the VFB voltage is regulated to the internal bandgap voltage. The current limit transconductance amplifier ILIM provides the secondary side average current limit function. The average voltage drops across the RSECSEN resistor is sensed and compared to the - 25mV threshold set by the internal ILIM amplifier. Once ILIM detects high output current, the current amplifier output pulls high, overrides the error amplifier, injects more current into the photo diode and forces a lower duty cycle. An RC network connected to the ICOMP pin is used to stabilize the secondary current limit loop. Alternatively, if only overcurrent fault protection is required, ICOMP can float. If under abnormal conditions the feedback path is broken, OVPIN provides another route for overvoltage fault protection. If the voltage at OVPIN is higher than the bandgap voltage, the OVP comparator forces OPTODRV high immediately. A simple external RC filter prevents a momentary overshoot at OVPIN from triggering the OVP comparator. Short OVPIN to ground if this pin is not used. The LTC1698 provides an open-drain PWRGD output. If VFB is less than 94% of its nominal value for more than 1ms, the PWRGD comparator pulls the PWRGD pin low. If VFB is higher than 94% of its nominal value for more than 2ms, the transistor MPWRGD shuts off, and an external resistor pulls the PWRGD pin high. The LTC1698 provides an auxiliary 3.3V logic power supply. This auxiliary power supply is externally compensated with a minimum 0.1F bypass capacitor. It supplies up to 10mA of current to any external devices.
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LTC1698
APPLICATIO S I FOR ATIO
Undervoltage Lockout
In UVLO (low VDD voltage) the drivers FG and CG are shut off and the pins OPTODRV, VAUX, PWRGD and ICOMP are forced low. The LTC1698 allows the bandgap and the internal bias currents to reach their steady-state values before releasing UVLO. Typically, this happens when VDD reaches approximately 4.0V. Beyond this threshold, the drivers start switching. The OPTODRV, VAUX, PWRGD and ICOMP pins return to their normal values and the chip is fully functional. However, if the VDD voltage is less than 7V, the OPTODRV and VAUX current sourcing capabilities are limited. See the OPTO driver graphs in the Typical Performance Characteristics section. VDD Regulator The bias supply for the LTC1698 is generated by peak rectifying the isolated transformer secondary winding. As shown in Figure 2, the zener diode Z1 is connected from base of Q5 to ground such that the emitter of Q5 is regulated to one diode drop below the zener voltage. RZ is selected to bring Z1 into conduction and also provide base current to Q5. A resistor (on the order of a few hundred ohms), in series with the base of Q5, may be required to surpress high frequency oscillations depending on Q5's selection. A power MOSFET can also be used by increasing the zener diode value to offset the drop of the gate-tosource voltage. VDD supply current varies linearly with the supply voltage, driver load and clock frequency. A 4.7F bypass capacitor for the VDD supply is sufficient for most applications. This capacitor must be large enough to provide a stable DC voltage to meet the LTC1698 VDD
VSECONDARY 1 D3 RZ 2k 0.47F Z1 10V
RB*
Q5 FZT690 VDD 4.7F
CG
1698 F04
*RB IS OPTIONAL, SEE TEXT
1698 F02
Figure 2. VDD Regulator
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supply requirement. Under start-up conditions, it must be small enough to power up instantaneously, enabling the LTC1698 to regulate the feedback loop. Using a larger capacitor requires evaluation of the start-up performance. SYNC Input Figure 3 shows the synchronous forward converter application. The primary controller LT3781 runs at a fixed frequency and controls MOSFETs Q1 and Q2. The secondary controller LTC1698 controls MOSFETs Q3 and Q4. An inexpensive, small-size pulse transformer T2 synchronizes the primary and the secondary controllers. Figure 4 shows the pulse transformer timing waveforms. When the LT3781 synchronization output SG goes low, MOSFET
L1 VOUT TG Q1 Q4 CG VIN PRIMARY CONTROLLER LT3781 D1
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*
D2
*
T1
SECONDARY CONTROLLER LTC1698 Q3
COUT
SG
BG
Q2
FG SYNC
*
CSG T2
*
CSYNC RSYNC
1698 F03
PRIMARY ISOLATION BARRIER
SECONDARY
Figure 3. Synchronization Using Pulse Transformer
TG BG SG
SYNC
FG
Figure 4. Primary Side and Secondary Side Synchronization Waveforms
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APPLICATIO S I FOR ATIO
drivers TG and BG go high. The pulse transformer T2 generates a negative slew at the SYNC pin and forces the secondary MOSFET driver FG to go high and CG to go low. When TG and BG go low, SG goes high and the secondary controller forces CG high and FG low. For a given pulse transformer, a bigger capacitor CSG generates a higher and wider SYNC pulse. The peak of this pulse should be much higher than the SYNC threshold. Amplitudes greater than 5V help to speed up the SYNC comparator and reduce the SYNC to FG and CG drivers propagation delay. The minimum pulse width is 75ns. Overshoot during the pulse transformer reset interval must be minimized and kept below the minimum comparator thresholds of 1V. The amount of overshoot can be reduced by having a smaller reset resistor RSYNC. For nonisolated applications, the SYNC input can be driven directly by a square pulse. To reduce the propagation delay, make the positive and negative magnitude of the square wave much greater than the 2.2V maximum threshold. In addition to the simple driver synchronization, the secondary controller requires a driver disable signal. Loss of synchronization while CG is high will cause Q4 to discharge the output capacitor. This produces a negative output voltage transient and possible damage to the load circuitry connected to VOUT. To overcome this problem, the LTC1698 comes with a unique adaptive time-out circuit. It works well within the 50kHz to 400kHz frequency range. At every positive SYNC pulse, the internal timer resets. If the SYNC signal is missing, the internal timer loses its reset command, and eventually exceeds the internal time-out limit. This forces both the FG and CG drivers to go low immediately. The time-out duration varies linearly with the LT3781 primary controller clocking frequency. Upon power up, the time-out circuitry takes a few clock cycles to adapt to the input clock frequency. During this time interval, the drivers pulse width might be prematurely terminated, and the inductor current flows through the MOSFETs body diode. Once the LTC1698 timer locks to the clocking frequency, the LTC1698 drivers follow the SYNC signal without fail. Figure 5 shows the SYNC time-out wave-
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SG SYNC FG CG RESET (INTERNAL) DISDRI (INTERNAL)
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Figure 5. SYNC Time-Out Waveforms
forms. The time-out circuit guarantees that if the SYNC pulse is missing for more than one period, both the drivers will be shut down preventing the output voltage from going below ground. The wide synchronization frequency range adds flexibility to the forward converter and allows this converter chip set to meet different application requirements. Under normal operating conditions, the time-out circuitry adapts to the switching frequency within a few cycles. Once synchronized, internal circuitry ensures the maximum time that the Catch FET (Q4) could be left turned on is typically just over one switching period. This is particularly important with high output voltages that can generate significant negative output inductor currents if the Catch FET Q4 is left on. Poor feedback loop performance including output voltage overshoot can cause the primary controller to interrupt the synchronization pulse train. While this generally is not a problem, it is possible that low frequency interruptions could lead to a time-out period longer than a switching period, limited only by the internal timer clamp (50s typical). Output Voltage Programming The switching regulator output voltage is programmed through a resistor feedback network (R1 and R2 in Figure 1) connected to VFB. If the output is at its nominal value, the divider output is regulated to the error amplifier threshold of 1.233V. The output voltage is thus set according to the relation: VOUT = 1.233 * (1 + R2/R1)
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APPLICATIO S I FOR ATIO
MARGIN Adjustment
The MARGIN input is used for adjusting the programmed output voltage linearly by varying the current flowing into and out of the pin. Forcing 100A into the pin moves the output voltage 5% higher. Forcing 100A out of the pin moves the output voltage 5% lower. With the MARGIN pin floating, the VFB pin is regulated to the bandgap voltage of 1.233V. The MARGIN pin is a high impedance input. It is important to keep this pin away from any noise source like the inductor switching node. Any stray signal coupled to the MARGIN pin can affect the switching regulator output voltage. This pin is internally connected to a 16.5k resistor that feeds the I-V converter. The I-V converter output linearly controls the error amplifier offset voltage. The input of the I-V converter is biased at 1.65V. This allows the 100A current to be obtained by connecting the MARGIN pin to the VAUX 3.3V supply (+ 5%) or GND (- 5%). For output voltage adjustment smaller than 5%, an external resistor REXT as shown in Figure 6 is added in series with the internal resistor to lower the current flowing into or out of the MARGIN pin. The value of REXT is calculated as follow: 5% REXT = - 1 * 16.5k REQUIRED %
REXT (OPTIONAL) 7 REDUCE VFB INCREASE VFB
RMARGIN MARGIN I-V CONVERTER
BANDGAP
VREF 5% VREF
VDD ERR VAUX 3.3V 0.1F 14 VAUX AUX GEN
+ -
VFB VCOMP 8 6
Figure 6. Output Voltage Adjustment
Overvoltage Function The OVPIN is used for overvoltage protection and is designed to protect against an open VFB loop. Opening the
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VFB loop causes the error amplifier to drive the OPTODRV pin low, forcing the primary controller to increase the duty cycle. This causes the output voltage to increase to a dangerously high level. To eliminate this fault condition, the OVP comparator monitors the output voltage with a resistive divider at OVPIN. A voltage at OVPIN higher than the VREF potential forces the OPTODRV pin high and reduces the duty cycle, thus preventing the output voltage from increasing further. The OVPIN senses the output voltage through a resistor divider network (R4 and R5 in Figure 1). The divider is ratioed such that the voltage at OVPIN equals 1.233V when the output voltage rises to the overvoltage level. The overvoltage level is set following the relation: VOVERVOLTAGE = 1.233 * (1 + R5/R4) The OVP comparator is designed to respond quickly to an overvoltage condition. A small capacitor from OVPIN to ground keeps any noise spikes from coupling to the OVP pin. This simple RC filter prevents a momentary overshoot from triggering the OVP comparator. The OVP comparator threshold is independent of the potential at the MARGIN pin. If the OVP function is not used, connect OVPIN to ground. Power Good The PWRGD pin is an open-drain output for power good indication. PWRGD floats if VFB is above 94% of the nominal value for more than 2ms. An external pull-up resistor is required for PWRGD to swing high. PWRGD pulls low if VFB drops below 94% of the nominal value for more than 1ms. The PWRGD threshold is referenced to the 1.233V bandgap voltage, which remains unchanged if the MARGIN pin is exercised. Opto Feedback and Frequency Compensation For a forward converter to obtain good load and line regulation, the output voltage must be sensed and compared to an accurate reference potential. Any error voltage must be amplified and fed back to the supply's control circuitry where the sensed error can be corrected. In an isolated supply, the control circuitry is frequently located on the primary. The output error signal in this type of
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LTC1698
APPLICATIO S I FOR ATIO
supply must cross the isolation boundary. Coupling this signal requires an element that will withstand the isolation potentials and still transfer the loop error signal. Optocouplers are widely used for this function due to their ability to couple DC signals. To properly apply them, a number of factors must be considered. The gain, or current transfer ratio (CTR) through an optocoupler is loosely specified and is a strong function of the input current through the diode. It changes considerably as a function of time (aging) and temperature. The amount of aging accelerates with higher operating current. This variation directly affects the overall loop gain of the system. To be an effective optical detector, the output transistor of the optocoupler must have a large base area to collect the light energy. This gives it a large collector to base capacitance which can introduce a pole into the feedback loop. This pole varies considerably with the current and interacts with the overall loop frequency compensation network. The common collector optocoupler configuration removes the miller effect due to the parasitic capacitance and
R * CTR (1 + s * C C * RC ) (1 + s * RK * C K ) 1 1 VC =- *5* * F * * (s * R2 * C C )* (1 + s * RC * C FB ) VOUT R * R RD + RK (1 + s * r * C DE ) (1 + s * RF * C F ) 1+ s * C K * K D RK + RD where: RD = Optocoupler diode equivalent small - signal resis tan ce CTR = Optocoupler current transfer ratio C DE = Optocoupler nonlinear capacitor across base to emitter = Optocoupler small - signal resis tan ce across the base emitter r
LTC1698 OPTODRV LT3781 VCC RK CK 100k MOC207 VCOMP CC RE RF CF CFB
1698 F07
+ -
VC
VREF VFB
Figure 7. Error Signal Feedback
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increases the frequency response. Figure 7 shows the optocoupler feedback circuitry using the common collector approach. Note that the terms RD, CTR, CDE and r vary from part to part. They also change with bias current. The dominant pole of the opto feedback is due to RF and CF. The feedforward capacitor CK at the optocoupler creates a low frequency zero. This zero should be chosen to provide a phase boost at the loop crossover frequency. The parallel combination of RK and RD form a high frequency pole with CK. For most optocouplers, RD is 50 at a DC bias of 1mA, and 25 at a DC bias of 2mA. The CTR term is the small signal AC current transfer ratio. For the QT Optoelectronics MOC207 optocoupler used here, the AC CTR is around 1, even though the DC CTR is much lower when biased at 1mA or 2mA. The first denominator term in the VC/VOUT equation has been simplified and assumes that CFB< C *C s * R2 * (C C + C FB )* 1 + s * RC * C FB C C + C FB
+ -
VREF 20k
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+ -
VREF VFB
VOUT R2
R1 RC
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LTC1698
APPLICATIO S I FOR ATIO
A series RC network can be added in parallel with R2 (Figure 7) to provide a zero for the feedback loop frequency compensation. The opto driver will drive a capacitive load up to 0.1F. For optocouplers with a base pin, switching signal noise can get into this high impedance node. Connect a large resistor, 1M or 2M between the base and the emitter. This increases the diode current and the overall feedback bandwidth slightly, and decreases the optocoupler gain. When designing the resistor in series with the optocoupler diode, it is important to consider the part to part variations in the current transfer ratio and its reduction over temperature and aging. The bigger the biasing current, the faster the aging. The LTC1698 opto driver is designed to source up to 10mA of current and swing between 0.4V to (VDD - 2.5V). This should meet the design consideration of most optocouplers. Besides the voltage feedback function, the LTC1698 opto driver couples fault signals to the primary controller and prevents catastrophic damage to the circuit. Upon current limit or an overvoltage fault, the ILIM or OVP comparator overrides the error amplifier output and forces the OPTODRV pin high. This sources maximum current into the external optodiode and reduces the forward converter duty cycle. Average Current Limit The secondary current limit function is implemented by measuring the negative voltage across the current sense resistor RSECSEN. The current limit transconductance
+
5 VOUT RCILM CCILM 13 ICOMP 100k MILIM OPTODRV OPTO
VREF 20k VCOMP 25mV FG
-
ILIM
LTC1698
Figure 8. Secondary Average Current Limit
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RILIM 3k
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amplifier ILIM has a - 25mV threshold. As shown in Figure 8, if the secondary current is small, the ICOMP pin goes low and the transistor MILIM shuts off. The potential at VCOMP determines the OPTODRV output. If the secondary current is large, ICOMP pulls high and forces the transistor MILIM to turn on hard. Thus the current limit circuit overrides the voltage feedback and forces OPTODRV high and injects maximum current into the external optocoupler. The RILIM resistor provides a linear relationship between the current sensed and the OPTODRV output. The ISNS and ISNSGND pins allow a true Kelvin current sense measurement and offer true differential measurement across the sense resistor. A differential lowpass filter formed by R6 and C2 removes the pulse-to-pulse inductor current ripple and generates the average secondary current which is equal to the load current. The lowpass corner frequency is typically set to 1 to 2 orders of magnitude below the switching frequency and follows the relationship:
25mV ILMAX 1 R6 = fSW 2 * * C2 * 10 RSECSEN =
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where: RSECSEN = Secondary current sense resistor ILMAX = Maximum allowed secondary current fSW = Forward converter switching frequency
DRIVE CG 2 Q4 T1
16 R6 12 C2 RDIV (OPTIONAL) R6
Q3
+
ISNS
ISNSGND
RSECSEN
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1698 F08
LTC1698
APPLICATIO S I FOR ATIO
If the application generates a bigger current sense voltage, a potential divider can be easily obtained by adding a resistor across C2. With this additional resistor, the voltage sensed by the current comparator becomes:
RDIV * VRSENSE RDIV + (2 * R6)
An RC network formed by RCILM and CCILM between ICOMP and VOUT can be used to stabilize the current limit loop. Connecting the compensation network to VOUT minimizes output overshoot during start-up or short-circuit recovery. The RCILM and CCILM zero should be chosen to be well within the closed-loop crossover frequency. This pin can be left floating if current loop compensation is not required. The forward converter secondary current limit function can be disabled by shorting ISNS and ISNSGND to ground. Auxiliary 3.3V Logic Power Supply An internal P-channel LDO (low dropout regulator) produces the 3.3V auxiliary supply that can power external devices or drive the MARGIN pin. This supply can source up to 10mA of current and the current limit is provided internally. The pin requires at least a 0.1F bypass capacitor. MOSFET Selection Two logic-level N-channel power MOSFETs (Q3 and Q4 in Figure 1) are required for most LTC1698 circuits. They are selected based primarily on the on-resistance and body diode considerations. The required MOSFET RDS(ON) should be determined based on input and output voltage, allowable power dissipation and maximum required output current. The average inductor (L1) current is equal to the output load current. This current is always flowing through either Q3 or Q4 with the power dissipation split up according to the duty cycle:
VOUT NP * VIN NS V N DC (Q 4) = 1 - OUT * P VIN NS DC (Q 3) =
where NP/NS is the turns ratio of the transformer T1.
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The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R.
PMAX(Q3) = IMAX * RDS(ON)Q3 * DC (Q 3) RDS(ON)Q3 =
2 2
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PMAX(Q3) IMAX * DC (Q 3)
2
PMAX(Q4) = IMAX * RDS(ON)Q4 * DC (Q 4) RDS(ON)Q4 = PMAX(Q4) IMAX * DC (Q 4)
2
where IMAX is the maximum load current and PMAX is the allowable conduction loss. In a typical 2-transistor forward converter circuit, the duty cycle is less than 50% to prevent the transformer core from saturating. This results in the duty cycle of Q4 being greater than that of Q3. Q4 will dissipate more power due to the higher duty cycle. A lower RDS(ON) MOSFET can be used for Q4. This will slow down the turn-on time of Q4 since a lower RDS(ON) MOSFET will have a larger gate capacitance. The next consideration for the MOSFET is the characteristic of the body diode. The body diodes conduct during the power-up phase, when the LTC1698 VDD supply is ramping up and the time-out circuit is adapting to the SYNC input frequency. The CG and FG signals terminate prematurely and the inductor current flows through the body diodes. The body diodes must be able to take the comparable amount of current as the MOSFETs. Most power MOSFETs have the same current rating for the body diode and the MOSFET itself. The LTC1698 CG and FG MOSFET drivers will dissipate power. This will increase with higher switching frequency, higher VDD or larger MOSFETs. To calculate the driver dissipation, the total gate charge Qg is used. This parameter is found on the MOSFET manufacturers data sheet. The power dissipated in each LTC1698 MOSFET driver is: PDRIVER = Qg * VDD * fSW where fSW is the switching frequency of the converter.
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APPLICATIO S I FOR ATIO
Power Transformer Selection
The forward transformer provides DC isolation and delivers energy from the primary to the secondary. Unlike the flyback topology, the transformer in the forward converter is not an energy storage device. As such, ungapped ferrite material is typically used. Select a power material rated with low loss at the switching frequency. Many core manufacturers have selection guides and application notes for transformer design. A brief overview of the more important design considerations is presented here. For operating frequencies greater than 100kHz, the flux in the core is usually limited by core loss, not saturation. It is important to review both criteria when selecting the transformer. The AC operating flux density for core loss is given by:
B AC = VIN * DC * 108 2 * NP * Ae * fSW
where: BAC is the AC operating flux density (gauss) DC is the operating duty cycle Ae is the effective cross sectional core area (cm2) fSW is the switching frequency To prevent core saturation during a transient condition, the peak flux density is:
BPK = VIN(MAX) * DC (MAX)* 108 NP * Ae * f SW
The minimum secondary turns count is:
NS(MIN) VOUT + VD = NP * VIN(MIN)* D C (MAX)
tOFF(MAX) =
where: VOUT is the secondary output voltage VD is the voltage drop across the rectifier in the secondary VIN(MIN) is the minimum input voltage DC(MAX) is the maximum duty cycle
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The core must be sized to provide sufficient window area for the amount of wire and insulation needed. The best performance is achieved by making each winding a single layer evenly distributed across the width of the bobbin. Multiple layers may be used to increase the copper area. Interleaving the primary and secondary windings will decrease the leakage inductance. In a single-ended forward converter, much of the energy stored in the leakage inductance is dissipated in the primary-side MOSFET during turn-off. It is good design practice to sandwich the secondary winding between two primary windings. For the 2-transistor forward converter shown in Figure 1, energy stored in the leakage inductance is returned to the input by diodes D1 and D2. With this topology, additional insulation for higher isolation can be used without significant penalty. For a more detailed discussion on transformer core and winding losses, see Application Note AN19. Inductor Selection The output inductor in a typical LTC1698 circuit is chosen for inductance value and saturation current rating. The output inductor in a forward converter operates the same as in a buck regulator. The inductance sets the ripple current, which is commonly chosen to be 40% of the full load current. Ripple current is set by:
IRIPPLE = VOUT * tOFF(MAX) L
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where:
(1- DC (MIN))
fSW
and DC(MIN) is calculated based on the maximum input voltage.
DC (MIN) = NP V * OUT NS VIN(MAX)
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Once the value of the inductor has been determined, an inductor with sufficient DC current rating is selected. Core saturation must be avoided under all operating conditions. Under start-up conditions, the converter sees a short circuit while charging the output capacitor. If the inductor saturates, the peak current will dramatically increase. The current will be limited only by the primary controller minimum on time and the circuit impedances. High efficiency converters generally cannot afford the core loss found in low cost iron powder cores, forcing the use of more expensive ferrite, molypermalloy, or Kool M(R) cores. As inductance increases, core loss goes down. Increased inductance requires more turns of wire so copper losses will increase. The optimum inductor will have equal core and copper loss. Ferrite designs have very low core losses and are preferred at higher switching frequencies. Therefore, design goals concentrate on minimizing copper loss and preventing saturation. Kool M is a very good, low-loss powder material with a "soft" saturation characteristic. Molypermalloy is more efficient at higher switching frequencies, but is also more expensive. Surface mount designs are available from many manufacturers using all of these materials. Output Capacitor Selection The output capacitor selection is primarily determined by the effective series resistance (ESR) to minimize voltage ripple. In a forward converter application, the inductor current is constantly flowing to the output capacitor, therefore, the ripple current at the output capacitor is small. The output ripple voltage is approximately given by:
1 VRIPPLE IRIPPLE * ESR + 8 * fSW * C OUT
The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. Typically, once the ESR requirement for COUT has been satisfied the capacitance is adequate for filtering and has the required RMS current rating.
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Fast load current transitions at the output will appear as a voltage across the ESR of the output capacitor until the feedback loop can change the inductor current to match the new load current value. As an example: at 3.3V out, a 10A load step with a 0.01 ESR output capacitor would experience a 100mV step at the output, a 3% output change. In surface mount applications, multiple capacitors may have to be placed in parallel to meet the ESR requirement. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1698. These items are also illustrated graphically in Figure 9. Check the following for your layout: 1. Keep the power circuit and the signal circuit segregated. Place the power circuit, shown in bold, so that the two MOSFET drain connections are made directly at the transformer. The two MOSFET sources should be as close together as possible. 2. Connect PGND directly to the sense resistor with as short a path as possible. The MOSFET gate drive return currents flow through this connection. 3. Connect the 4.7F ceramic capacitor directly between VDD and PGND. This supplies the FG and CG drivers and must supply the gate drive current. 4. Bypass the VAUX supply with a 0.1F ceramic capacitor returned to GND. 5. Place all signal components in close proximity to their associated LTC1698 pins. Return all signal component grounds directly to the GND pin. One common connection can be made to VOUT+ from R2, R5 and CCILM. 6. Make the connection between GND and PGND right at the LTC1698 pins. 7. Use a Kelvin-sense connection from the ISNS and ISNSGND pins to the secondary-side current-limit resistor RSECSEN.
Kool M is a registered trademark of Magnetics, Inc.
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APPLICATIO S I FOR ATIO
T1
L1
*
*
1 Q3 Q4 RSECSEN
D3 C4 T2
*
*
R7
R2
RK MOC207 CK R1 RC CC CFB
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 9. LTC1698 Layout Diagram
L1 VIN 36V TO 72V VCC BIAS 10k VDD VCC BOOST SYNC GBIAS 10pF LT3710 VFB FG ISNS LTC1698 10k 180pF TG BG LT3781 SG 0.01F CS 680pF CSET TG 0.1F SW ILCOMP BG SS BGS PGND VFB CL- CL+ VAOUT 3.3k 33nF 2.32k 3.01k 220 Q2 B340A 4700pF Q1 L2 1.8H 0.006 4.7F CMDSH-3 VCOMP CG
*
*
*
*
SYNC
OPTODRV VC + - VREF VFB GND
ISOLATION BOUNDARY
Figure 10. Simplified Single Secondary Winding 3.3V and 1.8V Output Isolated DC/DC Converter
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VOUT+
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+
COUT
VOUT -
1 2 4.7F 3
VDD LTC1698 CG
FG SYNC VAUX ICOMP ISNS ISENSGND PWRGD OVPIN
16 15 14 13 12 11 10 9 0.1F
CCILM
RCILM
R5
PGND 4 GND 5 6 7 8 OPTODRV VCOMP MARGIN VFB
1k 0.1F 1k
0.1F
R4
1698 F09
VOUT1 3.3V AT 10A
+
VOUT2 1.8V AT 10A COUT2
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COUT2: POSCAP, 680F/4V L2: SUMIDA CEP125-IR8MC-H Q1, Q2: SILICONIX Si7440DP
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VIN+ 36V TO 72V B2100 Si7456DP Si7456DP T1 PULSE PA0285 VOUT+ 5V /30A 0 PULSE PA0265 VOUT
0.56H DO1813P-561HC
1
*
1000pF 100V
*
7 10 1/4W
470F 6.3V POSCAP
1.5F 100V B2100 VCC 2 FMMT619 Si7456DP Si7884DP Si7884DP 4 1000pF 100V 10 1/4W 5
+ + +
22F 6.3V
470F 6.3V POSCAP
1.5F 100V
+
*
Si7456DP
470F 6.3V Si7884DP Si7884DP Si7884DP POSCAP
470F 6.3V POSCAP
TYPICAL APPLICATIO S
100 3 3.3 2200pF 250VAC VCC BAS21
0.008 1%, 1W
VIN-
VOUT- RTN
VIN
20k 0 B0540W 100 0.25W FZT690B ZVN3310F 4.7F 16V BAT54 VCC 0.1F 100V BAT54S 0.047F 4 220pF 1* 7 470 T2 PULSE ENG P2033 1F 16V 1 15 1k 7 3k 5VREF 10 3300pF 0.1F 1k 6 5 8 MOC207 2 VOUT 2200pF 43 1 4700pF 14 VAUX 0.1F PGND 3 GND 4 5 VDD SYNC OPTODRV LTC1698 12 ISNS 11 ISNSGND FG 16 330pF 10k MMBZ5240B 2k 0.25W 10
1mH DO1608C-105 COILCRAFT BAS21
FZT853
5241B 11V
VCC
B0540W
0.22F 50V
VCC
VIN
1000pF
VOUT
270k 0.25W
73.2k 1%
0.022F
3.3k 2 CG 6 VCOMP VFB OVPIN MARGIN PWRGD 10 ICOMP 8 9 7 13
4.22k 1%
BAS21
3.01k 1%
MMBD4148
*8
ON/OFF 6 8 10 2.43k 1% 0 3 7 4
20 18 19 15 11 14 13 VCC VBST BSTREF TG BG SENSE PGND 12 2 SG OVLO LT3781 1 SHDN 9 5VREF FSET THERM SYNC SS SGND VC VFB
5VREF RT1 100k 82pF 0.01F
5
VOUT TRIM 1.24k 1%
1F
1000pF
1.24k 1%
52.3k 1%
4.7F 16V
10k
976 1%
1F
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LTC1698
19
Figure 11. 36VIN-72VIN to 5V/30A Isolated Synchronous Forward Converter
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FMMT718
*
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1 MURS120 MURS120 6 2 1000pF 100V 330F 6.3V KEMET T520
*
*
*
TYPICAL APPLICATIO S
MMBT3906 0.03 3.3 VCC BAS21 BAS21 4.7 ZETEX ZVN3310F BAT54 MBR0540 1k 330pF 0.22F FZT690B 9V 100 10k 2k 1 VIN 62k 1/4W 1mH DO1608C-105 COILCRAFT 2200pF 250V 10 1/4W
3
10 1/4W
VIN-
VOUT-
100 1/4W
100 1/4W
VOUT 100 1/4W +SENSE 9V 5 3.01k 1%
FQT7N10L
VCC
18V MMBZ5248B
5VREF MMBD914
47k
+
LT1783CS5 3.01k 2 1% 1k 1000pF
3 3.01k 1% -SENSE
MMBT3904
4.7F
-
4
OPTIONAL FAST START* VCC 10V MMBZ5240B 0.1F 0.1F BAT54 220pF 1* BAT54 8 5VREF 43 1 1k 14 3300pF 10 5 8 82pF 0.01F 4700pF 1k MOC207 2 4700pF 7 6 5 PULSE ENG PA0184 4.7F
3.01k 1%
100 1/4W
VIN
OPTIONAL DIFFERENTIAL SENSE** 0.1F 0.022F 1k 1 470 15 5 OPTODRV LTC1698 OVPIN MARGIN VAUX 0.1F SYNC 12 VDD ISNS 11 ISNSGND 16 2 FG CG 6 VCOMP VFB 8 9 7 ICOMP 13 PGND 3 GND 4 PWRGD 10 1.78k 1% 1k VOUT+ 0.22F 1.24k 1%
1698 F12
VCC
270k 1/4W
73.2k 1%
ROUT (OPTIONAL) VOUT+ 3.01k 1% 2.43k 1%
RIN (OPTIONAL) 20 18 19 17 16 15 11 12
BAS21
*4
ON/OFF
13 VCC VBST BSTREF TG NC NC BG SENSE SG 14 2 PGND OVLO LT3781 1 SHDN 9 THERM SYNC SS SGND VC VFB 5VREF FSET 5 3k 10k 6 3 7 8 4 10
+ 100F
52.3k 1% RT1 100k 2.43k 1%
10k
5VREF
TRIM
20V
0.1F
1000pF
3300pF
1.24k 1%
1F
Figure 12. LT3781/LTC1698 36VIN-72VIN to 3.3V/15A Isolated Synchronous Forward Converter-Quarter Brick
U
20
10 MMBT3906 7 8 Si7456DP T1 38431 SCHOTT VOUT+ 5
3.3H D01608C-332 COILCRAFT
VIN
LTC1698
VIN+
0.82F 100V
+
+
0.82F 100V x2 10 Si7456DP 4 Si7892DP Si7892DP 1000pF 100V 330F 6.3V + KEMET Si7892DP Si7892DP T520
330F 6.3V KEMET T520
+
330F 6.3V KEMET T520
1698f
VIN+ 10 SUD40N10-25 SUD40N10-25 12 11 MURS120T3 MURS120T3 4 VTOP T1 3 EFD25 VOUT+ 22 0.25W 470pF 100V 25H MAG INC CORE 55380-A2 18T #18AWG
4.7H DO1608C-472 COILCRAFT VIN
* *
1.5F 100V 1.5F 100V
1.5F 100V
+ +
68F 25V AVX 68F 25V AVX
8 7 10 6 1
470pF 100V
*
10
SUD40N10-25 5
NC
22 0.25W 68F 25V AVX
+
+
*
TYPICAL APPLICATIO S
9 Si4486EY x2 Si4486EY x2 VOUT- 0.015 10 0.25W MURS120T3 3.3
2 0.025 1/2W
VIN- VCC BAS21LT1 BAS21LT1 2200pF 250V 1mH DO1608C-105 COILCRAFT VTOP ZVN3310F 0.22F 50V FZT603 ZETEX 4.7F 16V BAT54 200 330pF 100pF VCC BAT54 47 3 BAT54 1* 4 1k T2 0.01F 50V MIDCOM, INC 31264R 10k 10V MMBZ5240BLT1 20k 0.25W 100 0.25W
T1 EFD25-3F3 LP = 120H 2mil GAP EACH LEG 2M POLYESTER FILM
PINS 9-10 5T BIFILAR 33AWG PINS 2-5 12T BIFILAR 33AWG PINS 4-3 7T QUADFILAR 26AWG PINS 7,8-11,12 12T BIFILAR 24AWG PINS 6-4 8T QUADFILAR 26AWG 0.1F 100V VTOP
BAT54
VCC
SQUARE 0.031 INCH MARGIN TAPE
1000pF
BAS21LT1
15V MMBZ5245BLT1
0.022F
VIN
3.3k 1 16 2 6
VOUT+ 8.25k 0.1%
20k
*6
220pF 10k 15 5 1k SYNC
270k 0.25W 5VREF 7 6 5 3300pF 1k 8 2
73.2k 1%
VDD OPTODRV
FG
CG
VCOMP VFB LTC1698 OVPIN
8 9
12 13 20 18 19 17 16 11 14 VCC VBST BSTREF TG BLKSENS BG SENSE IMAX SG 15 2 PGND OVLO LT3781 1 SHDN 9 5VREF FSET THERM SYNC SGND VC VFB SS ISO1 MOC207 431 5 6 8 3k 10 3 7 4 52.3k 1% 10 4700pF 82pF
0.1F 50V
+
10k
56k
5VREF
1k 4700pF VOUT+ 0.01F 909 0.1% 0.1F 50V 0.1F 50V 215 0.1F 215
1698 F13
68F 25V
7 MARGIN ICOMP 13 VAUX ISNS ISNSGND PGND GND PWRGD 14 12 11 3 4 10
0.33F 50V
1000pF
24k
1.24k 1%
1F 25V
110
0.033F
UNLESS NOTED: ALL PNPs MMBT39O6LT1
18V MMBZ5248BLT1
VOUT-
LTC1698
21
Figure 13. 36VIN-72VIN to 12V/5A Isolated Synchronous Forward Converter
U
68F 25V AVX
1698f
LTC1698
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP .053 - .068 (1.351 - 1.727) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
22
U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 TYP .008 - .012 (0.203 - 0.305) .0250 (0.635) BSC
GN16 (SSOP) 0502
1698f
LTC1698
PACKAGE DESCRIPTIO
S Package 16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.045 .005 .050 BSC N 16 15 14
.245 MIN
1 .030 .005 TYP
2
3
N/2
RECOMMENDED SOLDER PAD LAYOUT 1 .010 - .020 x 45 (0.254 - 0.508) .053 - .069 (1.346 - 1.752) 0 - 8 TYP 2 3 4 5 6 7 8
.008 - .010 (0.203 - 0.254)
.016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
.386 - .394 (9.804 - 10.008) NOTE 3 13 12 11 10 9 N .160 .005 .228 - .244 (5.791 - 6.197) N/2 .150 - .157 (3.810 - 3.988) NOTE 3 .004 - .010 (0.101 - 0.254) .014 - .019 (0.355 - 0.483) TYP .050 (1.270) BSC
S16 0502
1698f
23
LTC1698
TYPICAL APPLICATIO S
LT3781/LTC1698 Isolated 3.3V/15A Converter LT3781/LTC1698 Isolated 5V/30A Converter Efficiency vs Load Current
95 90 VIN = 36V VIN = 48V
EFFICIENCY (%)
TOP
LT3781/LTC1698 Isolated 3.3V/15A Converter
EFFICIENCY (%)
BOTTOM
RELATED PARTS
PART NUMBER LT1339 LT1425 LT1431 LT1680 LT1681 LT1725 LT1737 LT3710 LT3781 DESCRIPTION High Power Synchronous DC/DC Controller Isolated Flyback Switching Regulator Programmable Reference High Power DC/DC Step-Up Controller Dual Transistor Synchronous Forward Controller General Purpose Isolated Flyback Controller High Power Isolated Flyback Controller Secondary Side Synchronous Post Regulator Dual Transistor Synchronous Forward Controller COMMENTS Operation Up to 60V Maximum General Purpose with External Application Resistor 0.4% Initial Voltage Tolerance Operation Up to 60V Maximum Operation Up to 72V Maximum Drives External Power MOSFET with External ISENSE Resistor Sense Output Voltage Directly from Primary-Side Winding Generates a Regulated Auxiliary Output in Isolated DC/DC Converters, Dual N-Channel MOSFET Synchronous Drivers Operation up to 72V Maximum
1698f
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
85 80 VIN = 72V 75 70 65
0
5
10 15 20 LOAD CURRENT (A)
25
30
1698 TA01
LT3781/LTC1698 Isolated 3.3V/15A Converter Efficiency vs Load Current
95 VIN = 36V
90
85 VIN = 48V
80
75 VIN = 72V 70 0 3 9 6 IOUT (XX) 12 15
1698 TA02
LT/TP 0203 2K * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2000

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